(a) Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same. More particularly, the present invention relates to a contact hole of a semiconductor device and a method for manufacturing the same.
(b) Description of the Related Art
Typically, a semiconductor device is insulated from another semiconductor device or an exterior circuit. For an electrical connection thereof, a contact hole is formed in an insulating layer, and a conductive material such as a metal fills the contact hole.
However, integrated circuit design rule dimensions decrease as Integration of semiconductor devices Increases, and thus, gaps between semiconductor device (or integrated circuit) patterns are reduced. Accordingly, contact hole aspect ratios also increase as integration of semiconductor devices increases.
Typically, a contact hole is formed by etching the insulating layer, and a contact failure may result when the insulating layer is not fully etched (e.g., such that part of the Insulating layer remains at the bottom of the contact hole). Therefore, a contact hole etching process may be performed to provide an overcut etch profile so as to prevent such a contact failure.
Hereinafter, a conventional method for forming a contact hole will be described in detail with reference to FIG. 1, FIG. 2A, and FIG. 2B.
Firstly, as shown In FIG. 1 and FIG. 2A a gate Insulating layer 11, a gate 12, and an Insulating spacer 13 are formed above a semiconductor substrate 10, and a source/drain junction region 14 is formed in the substrate 10. Then, a flowable interlayer insulating layer 15 such as a borophosphosilicate glass (BPSG) layer or a phosphosilicate glass (PSG) layer is formed over the substrate so as to fill the gap between the gates 12.
Subsequently, as shown in FIG. 2B (and in part in FIG. 1), the interlayer insulating layer 15 is etched to form a contact hole 16 partially exposing the junction region 14. In this case, the interlayer insulating layer 15 is performed such that contact hole 18 has an overcut etch profile and becomes fully open.
However, when the contact hole 16 has an overcut profile, the junction region 14 is also at least partially etched (although the contact hole 16 may become fully open without a remaining part of the interlayer insulating layer 15 at the bottom of the contact hole 16). Therefore, a thickness D1 from a contact surface at the bottom of the contact hole 16 to a bottom of the junction region 14 Is reduced, and accordingly, a contact resistance characteristic of a wire contacting the junction region 14 through the contact hole 16 may become substantially deteriorated.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention, and therefore It may contain information that does not form information (e.g., prior art) that may be already known In this or any other country to a person of ordinary skill in the art.